From f1d017401b0efef229a45d1b4ffeca95a287594b Mon Sep 17 00:00:00 2001
From: Jeffrey Armstrong <jeff@approximatrix.com>
Date: Wed, 6 Nov 2024 16:47:33 -0500
Subject: Initial commit with functioning CPU detection code

---
 asm/386q.asm | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 asm/386q.asm

(limited to 'asm')

diff --git a/asm/386q.asm b/asm/386q.asm
new file mode 100644
index 0000000..4496d66
--- /dev/null
+++ b/asm/386q.asm
@@ -0,0 +1,70 @@
+        push bp
+        mov bp, sp
+        
+        ; push zero onto the stack and pop it into flags.
+        ; some bits won't change
+        xor ax,ax
+        push ax
+        popf
+        pushf
+        pop ax
+        
+        and ax, 0xf000 ;0f000h
+        cmp ax, 0xf000 ;0f000h
+        je lessthantwoeightsix
+        
+        ; marked as 286 (2)
+        mov dl, 2
+        
+        mov ax, 0x7000 ;7000h
+        push ax
+        popf
+        
+        pushf
+        pop ax
+        and ax, 0x7000 ;7000h
+        jz alldone
+        
+        ; mark as 386 (3)
+        inc dl
+        
+        jmp alldone
+        
+lessthantwoeightsix:
+        
+        mov dl, 1
+        
+        mov al, 0xff ;0ffh
+        mov cl, 0x21 ;21h
+        shr al, cl
+        
+        ; if the shift leaves zero, it's a 8088 class cpu, else 80186/88
+        jnz alldone
+        
+        ; Lets see if we have a V20/V30 (V)
+        mov dl, 0x56 ;056h
+
+        sti
+        push si
+        
+        mov si, 0
+        mov cx, 0xffff ;0ffffh
+        ;rep lods [BYTE PTR es:si]
+        rep lodsb
+        
+        pop si
+        
+        or cx, cx
+        jz alldone
+        
+        ; mark as a 8088/8086 (0)
+        mov dl, 0
+        
+alldone:
+        ; store in ax
+        xor dh, dh
+
+        mov di, [bp]+6
+        mov [di], dx
+        pop bp
+        retf 2
\ No newline at end of file
-- 
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